Hello, I'm Rinse Wester, founder of Westpulse. I have a background in electrical engineering and computer science and a PhD from the University of Twente on design methodologies for FPGAs. Additionally, I have a strong affinity with model-based design delivering results using the right abstraction.
From bit-level FPGA hardware to high-level software.
FPGA hardware design, for both Altera and Xilinx FPGAs. Delivering solutions for digital signal processing and parallel computation.
From complex ideas to high-performance implementations. Experienced in, but not limited to, (Py)Qt, C(++) and Python.
Work has been done for the following companies: